Registered user since Sat 20 Dec 2025
Name:Yang Hu
Affiliation:Tsinghua University
Contributions
2026
HPCA
- MoEntwine: Unleashing the Potential of Wafer-scale Chips for Large-scale Expert Parallel Inference
- FACE: Fully PD Overlapped Scheduling and Multi-Level Architecture Co-Exploration on Wafer
- WATOS: Efficient LLM Training Strategies and Architecture Co-exploration for Wafer-scale Chip
- TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips
- ReThermal: Co-Design of Thermal-Aware Static and Dynamic Scheduling for LLM Training on Liquid-Cooled Wafer-Scale Chips
- HR-DCIM: \underline{H}igh-\underline{R}eliability Floating-Point \underline{D}igital \underline{CIM} Architecture with Unified Low-Cost Iterative Error Correction
- PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion
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