Verification is a critical process for ensuring the correctness of modern processors. The emergence of new instruction set architectures (ISAs), such as RISC-V, has introduced additional demands for more agile and efficient verification methodologies, particularly in terms of verification efficiency and better coverage. While conventional software-based approaches, particularly fuzz testing techniques adapted from software verification domains, demonstrate satisfactory coverage metrics, they exhibit critical limitations when applied to processor verification, including suboptimal performance and inadequate test case quality. Hardware-accelerated solutions employing FPGA or ASIC platforms have attempted to mitigate these issues through fuzzing integration, yet they confront persistent challenges encompassing host-FPGA communication overhead, inefficient test pattern generation, and suboptimal verification loop implementation.

In this paper, we present TurboFuzz—an end-to-end hardware-accelerated verification framework for processors. TurboFuzz fully implements a hardware-accelerated Test Generation-Simulation-Coverage Feedback loop on FPGAs. By optimizing test case (seed) control flow, inter-seed scheduling, and hybrid fuzzer integration, TurboFuzz enhances test quality, thereby improving coverage and loop execution efficiency. Furthermore, TurboFuzz employs a feedback-driven generation mechanism to accelerate coverage convergence. Experimental results demonstrate that, within the same time budget, the FPGA-accelerated end-to-end verification loop achieved up to $2.23\times$ more coverage collection than software-based fuzzers within the same time budget, and up to $571\times$ performance speedup when catching real-world issues, while maintaining full visibility and debugging capabilities with moderate area overhead.