Collaroy - HPCA 2026

VenueInternational Convention Centre Sydney

Room nameCollaroy

Floor3

Room numberC3.6

Capacity144

Room InformationNo extra information available

Program

This program is tentative and subject to change.

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Sat 31 Jan
Displayed time zone: Hobart change

	08:45 - 10:30	XiangShanWorkshops and Tutorials at Collaroy

	11:00 - 12:45	XiangShanWorkshops and Tutorials at Collaroy

	13:45 - 15:30	HPSmartNetWorkshops and Tutorials at Collaroy

	16:00 - 17:45	HPSmartNetWorkshops and Tutorials at Collaroy

Sun 1 Feb
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	08:45 - 10:30	MCCSysWorkshops and Tutorials at Collaroy

	11:00 - 12:45	MCCSysWorkshops and Tutorials at Collaroy

	13:45 - 15:30	MCCSysWorkshops and Tutorials at Collaroy

	16:00 - 17:45	MCCSysWorkshops and Tutorials at Collaroy

Mon 2 Feb
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09:50 - 11:10	Cache Coherence and Chiplet InterconnectsMain Conference at Collaroy

09:50 20m Talk		$C^3$ : CXL Coherence Controllers for Heterogeneous Architectures Main Conference David Schall Technical University of Munich, Anatole Lefort Technical University of Munich (TUM), Nicolò Carpentieri Technical University of Munich, Julian Pritzi Technical University of Munich, Soham Chakraborty TU Delft, Nicolai Oswald NVIDIA, Pramod Bhatotia TU Munich
10:10 20m Talk		Cohet: A CXL-Driven Coherent Heterogeneous Computing Framework with Hardware-Calibrated Full-System Simulation Main Conference Yanjing Wang National University of Defense Technology, Lizhou Wu National University of Defense Technology, Sunfeng Gao National University of Defense Technology, Yibo Tang National University of Defense Technology, Junhui Luo National University of Defense Technology, Zicong Wang National University of Defense Technology, Yang Ou National University of Defense Technology, Dezun Dong NUDT, Nong Xiao National University of Defense Technology & Sun Yat-sen University, Mingche Lai National University of Defense Technology
10:30 20m Talk		Supporting High-performance Write-through Cache-Coherence Protocols under TSO Main Conference Burak Ocalan University of Illinois Urbana-Champaign, Chloe Alverti University of Illinois at Urbana-Champaign, Shashwat Jaiswal University of Illinois Urbana-Champaign, USA, Antonis Psistakis University of Illinois Urbana-Champaign, David Koufaty Unaffiliated, Suyash Mahar UC San Diego, Steven Swanson University of California San Diego, Josep Torrellas University of Illinois at Urbana-Champaign
10:50 20m Talk		Deadlock-Free Bridge Module for Inter-Chiplet Communication in Open Chiplet Ecosystem Main Conference Zhiqiang Chen National University of Defense Technology, Wenwen Fu National University of Defense Technology, Yongwen Wang National University of Defense Technology, Hongwei Zhou National University of Defense Technology

11:30 - 12:50	DRAM Security and ReliabilityMain Conference at Collaroy

11:30 20m Talk		MIRZA: Efficiently Mitigating Rowhammer with Randomization and ALERT Main Conference Hritvik Taneja Georgia Tech, Ali Hajiabadi ETH Zurich, Michele Marazzi ABB Research, Kaveh Razavi ETH Zürich, Moinuddin K. Qureshi Georgia Tech
11:50 20m Talk		SALT: Track-and-Mitigate Subarrays, Not Rows, for Blast-Radius-Free Rowhammer Defense Main Conference Moinuddin K. Qureshi Georgia Tech
12:10 20m Talk		ReScue: Reliable and Secure CXL Memory Main Conference Chihun Song UIUC, Austin Antony Cruz UIUC, Michael Jaemin Kim Meta, Minbok Wi Seoul National University, Gaohan Ye UIUC, Kyungsan Kim Samsung Electronics, Sangyeol Lee Samsung Electronics, Jung Ho Ahn Seoul National University, Nam Sung Kim UIUC
12:30 20m Talk		Secret Caching Sauce for High-Performance Secure Memory Main Conference Xu Jiang Huazhong University of Science and Technology, Xueliang Wei Huazhong University of Science and Technology, YiFei Qu Huazhong University of Science and Technology, Dan Feng Huazhong University of Science and Technology, China, Yulai Xie Huazhong University of Science and Technology, Wei Tong Huazhong University of Science and Technology, China

14:10 - 15:30	Memory System ReliabilityMain Conference at Collaroy

14:10 20m Talk		Predicting DRAM Failures at Scale: A Two-Stage Approach for Heterogeneous Systems Main Conference Chenglin Wang Xiamen University, Shouxin Wang Xiamen University, Shuyue Zhou Xiamen University, Ronglong Wu Xiamen University, Zhirong Shen Xiamen University, Lu Tang Xiamen University, Yiming Zhang Xiamen University, Jialiang Yu Huawei, Min Zhou Huawei
14:30 20m Talk		MemSOS: OS-Guided Selective Memory Mirroring Main Conference Junghoon Kim Seoul National University & Samsung Electronics, Jongheon Jeong Seoul National University, Seokwon Moon Seoul National University, Seong Hoon Seo Seoul National University, Yeonhong Park Seoul National University, Jinkyu Jeong Yonsei University, Nam Sung Kim UIUC, Jae W. Lee Seoul National University
14:50 20m Talk		ASPA: Reassigning DDR5 Parity Bandwidth Main Conference Fan Li University of Central Florida, Qiufeng Li George Washington University, Yanan Guo University of Rochester, Weidong Cao George Washington University, Xin Xin University of Central Florida
15:10 20m Talk		HR-DCIM: \underline{H}igh-\underline{R}eliability Floating-Point \underline{D}igital \underline{CIM} Architecture with Unified Low-Cost Iterative Error Correction Main Conference Zhen He Tsinghua University, Yiqi Wang Tsinghua University, Zhiheng Yue Tsinghua University, Zihan Wu Tsinghua University, Huiming Han Tsinghua University, Shaojun Wei Tsinghua University, Yang Hu Tsinghua University, Fengbin Tu The Hong Kong University of Science and Technology, Shouyi Yin Tsinghua University

15:50 - 17:10	Processing-in-Memory ArchitecturesMain Conference at Collaroy

15:50 20m Talk		The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory Execution Main Conference Minh S. Q. Truong Carnegie Mellon University, Yiqiu Sun University of Illinois Urbana-Champaign, Dawei Xiong University of Illinois Urbana-Champaign, Amol Shah University of Illinois Urbana-Champaign, Alex Glass Carnegie Mellon University, Abraham Farrell University of Illinois Urbana-Champaign, James A. Bain Carnegie Mellon University, L. Richard Carley Carnegie Mellon University, Saugata Ghose University of Illinois Urbana-Champaign
16:10 20m Talk		CoCoTree: A Computation-Capable Architecture for Collective Communication in Scalable PIM Main Conference Shunchen Shi Institute of Computing Technology, Chinese Academy of Sciences ; University of Chinese Academy of Sciences, Qijia Yang Institute of Computing Technology, Chinese Academy of Sciences ; University of Chinese Academy of Sciences, Fan Yang Institute of Computing Technology, Chinese Academy of Science, Yu Huang Huazhong University of Science and Technology, Youwei Zhuo Peking University, Zhichun Li Institute of Computing Technology, Chinese Academy of Sciences ; University of Chinese Academy of Sciences, Ninghui Sun State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences, Xueqi Li State Key Lab of Processors, Institute of Computing Technology, CAS
16:30 20m Talk		PIM-malloc: A Fast and Scalable Dynamic Memory Allocator for Processing-In-Memory (PIM) Architectures Main Conference Dongjae Lee KAIST, Bongjoon Hyun Samsung, Youngjin Kwon KAIST, Minsoo Rhu KAIST
16:50 20m Talk		Count2Multiply: Reliable In-Memory High-Radix Counting Main Conference Joao Paulo Cardoso de Lima TU Dresden, ScaDS.AI, Benjamin F. Morris III Duke University, Asif Ali Khan TU Dresden, Germany, Jeronimo Castrillon TU Dresden, Germany, Alex Jones Syracuse University

Tue 3 Feb
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09:50 - 11:10	CPU Microarchitecture OptimizationMain Conference at Collaroy

09:50 20m Talk		The Last-Level Branch Predictor Revisited Main Conference David Schall Technical University of Munich, Mária Ďuračková University Of Edinburgh, Boris Grot University of Edinburgh, UK
10:10 20m Talk		Tempranillo: Non-Speculative Early Register Release Main Conference Carlos Escuin Computing Systems Lab, Huawei Technologies Switzerland AG, Paolo Salvatore Galfano Computing Systems Laboratory, Zurich Research Center, Huawei Technologies, Switzerland, Davide Basilio Bartolini Computing Systems Laboratory, Zurich Research Center, Huawei Technologies, Switzerland, Leeor Peled Boole Labs, Tel-Aviv Research Center, Huawei Technologies, Israel, Mehdi Alipour Computing Systems Laboratory, Zurich Research Center, Huawei Technologies, Switzerland
10:30 20m Talk		SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in Datacenters Main Conference Sanghyun Kim Sungkyunkwan University, Jinhyeok Oh Sungkyunkwan University, Taehun Kim Sungkyunkwan University, Gyutae Kim Sungkyunkwan University, Youngsok Kim Yonsei University, Jaehyun Hwang Sungkyunkwan University, Joonsung Kim Sungkyunkwan University
10:50 20m Talk		I-POP: Ignite Positive Prefetchers Main Conference Yiquan Lin Zhejiang University and Alibaba Group, Wenhai Lin Alibaba Group, Yiquan Chen Alibaba Group, Jiexiong Xu Zhejiang University and Alibaba Group, Shishun Cai Alibaba Group, Jiarong Ye Zhejiang University, Zonghui Wang Zhejiang University, Wenzhi Chen Zhejiang University

11:30 - 12:50	Caching and PrefetchingMain Conference at Collaroy

11:30 20m Talk		Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning Main Conference Zhenrong Lang ETH Zürich, Rahul Bera ETH Zurich, Caroline Hengartner ETH Zürich, Konstantinos Kanellopoulos ETH Zurich, Rakesh Kumar NTNU, Mohammad Sadrosadati ETH Zürich, Onur Mutlu ETH Zurich
11:50 20m Talk		Streamlined On-Chip Temporal Prefetching Main Conference Quang Duong The University of Texas at Austin, Calvin Lin University of Texas, Austin
12:10 20m Talk		Intermittence-Aware Cache Compression Main Conference Gan Fang Purdue University, Jianping Zeng Arizona State University, Yuchen Zhou Purdue University, Changhee Jung Purdue University, USA
12:30 20m Talk		SnakeMan: Applying Relation-centric Notation to Model and Optimize Data Swizzle in the Cache of Modern NPU Main Conference Hanyu Zhang Zhejiang University, Fangxu Guo Zhejiang University, Liqiang Lu Zhejiang University, Long Wang Huawei Technologies, Yunfei Du Huawei Technologies, Zhe Wang Huawei Technologies, Jinghan Zhang Huawei Technologies, Jie Zhang Peking University, Chenli Xue Zhejiang University, Chengpeng Wu Zhejiang University, Ziyi Zhang Zhejiang University, Eric Liang Peking University, Size Zheng ByteDance, Jianwei Yin Zhejiang University

14:10 - 15:30	Memory Systems for Scalable ComputingMain Conference at Collaroy

14:10 20m Talk		BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism Main Conference Suhas Vittal Georgia Tech, Moinuddin K. Qureshi Georgia Tech
14:30 20m Talk		RoMe: Row Granularity Access Memory System for Large Language Models Main Conference Hwayong Nam Seoul National University, Michael Jaemin Kim Meta, Seungmin Baek Seoul National University, Jumin Kim Seoul National University, Jung Ho Ahn Seoul National University
14:50 20m Talk		HDPAT: Hierarchical Distributed Page Address Translation for Wafer-Scale GPUs Main Conference daoxuan xu William & Mary, Ying Li William & Mary, Yuwei Sun UIUC, Jie Ren William & Mary, Yifan Sun William&Mary
15:10 20m Talk		Pulse: Fine-Grained Hierarchical Hashing Index for Disaggregated Memory Main Conference Guangyang Deng Xiamen University, Zixiang Yu Xiamen University, Zhirong Shen Xiamen University, Qiangsheng Su Xiamen University, Jiwu Shu Xiamen University

15:50 - 17:10	Accelerator Design and ModelingMain Conference at Collaroy

15:50 20m Talk		NPUWattch: ML-based Power, Area, and Timing Modeling for Neural Accelerators Main Conference Sehyeon Kim Yonsei University, Minkwan Kim Yonsei University, Chanho Park Yonsei University, Hanmok Park Kyungpook National University, Seonghoon Kim Kyungpook National University, Taigon Song Kyungpook National University, William Song Yonsei University
16:10 20m Talk		Area Bloating and the Future of Specialization Main Conference Qixuan Yu Princeton University, David Wentzlaff Princeton University
16:30 20m Talk		Advancing Full-stack Acceleration for Schrödinger-Style Quantum Simulation Main Conference Shuang Liang Imperial College London, Yuncheng Lu Imperial College London, Ce Guo Imperial College London, Paul H J Kelly Imperial College London, Wayne Luk Imperial College London, Hongxiang Fan Imperial College London
16:50 20m Talk		COMET: Communication and Memory Co-Design for Fine-Grained AI Inference in MCM Accelerators Main Conference Taishu Sheng College of Computer Science and Technology, National University of Defense Technology, Guangyu Sun Peking University, Dezun Dong NUDT

Wed 4 Feb
Displayed time zone: Hobart change

09:50 - 11:10	Hardware Security and Side-Channel DefensesMain Conference at Collaroy

09:50 20m Talk		DSASSASSIN: Cross-VM Side-Channel Attacks by Exploiting Intel Data Streaming Accelerator Main Conference Ben Chen The Hong Kong University of Science and Technology (Guangzhou), Kunlin Li The Hong Kong University of Science and Technology (Guangzhou), Shuwen Deng Tsinghua University, Dongsheng Wang Tsinghua University, Yun Chen The Hong Kong University of Science and Technology (Guangzhou)
10:10 20m Talk		SSBleed: Non-speculative Side-channel Attacks via Speculative Store Bypass on Armv9 CPUs Main Conference Chang Liu Tsinghua University, Hongpei Zheng Tsinghua University, Xin Zhang Peking University, Dapeng Ju Tsinghua University, Dongsheng Wang Tsinghua University, Yinqian Zhang Southern University of Science and Technology, Trevor E. Carlson National University of Singapore
10:30 20m Talk		Protean: A Programmable Spectre Defense Main Conference Nicholas Mosier Stanford University, Hamed Nemati KTH Royal Institute of Technology, John C. Mitchell Stanford University, Caroline Trippel Stanford University
10:50 20m Talk		HERO-Sign: Hierarchical Tuning and Efficient Compiler-Time GPU Optimizations for SPHINCS$^+$ Signature Generation Main Conference Yaoyun Zhou University of California, Merced, Qian Wang University of California, Merced (UC Merced)

11:30 - 12:50	FPGA, SmartNIC, and Reconfigurable ComputingMain Conference at Collaroy

11:30 20m Talk		RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs Main Conference Hongshi Tan National University of Singapore, Yao CHEN , Xinyu Chen Hong Kong University of Science and Technology, Qizhen Zhang University of Toronto, Cheng Chen ByteDance, China, Weng-Fai Wong National University of Singapore, Bingsheng He National University of Singapore
11:50 20m Talk		DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics Main Conference Anshu Gupta UC San Diego, Yingqi Cao UC San Diego, Jason Liang UC San Diego, Yatish Turakhia UC San Diego
12:10 20m Talk		Sassy: SmartNIC-Assisted Notification Delivery for μs-scale RDMA Workloads Main Conference Hamed Seyedroudbari Georgia Tech, Alexandros Daglis Georgia Tech
12:30 20m Talk		TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification Main Conference Yang Zhong Institute of Computing, Chinese Academy of Sciences, Haoran Wu University of Cambridge, Xueqi Li State Key Lab of Processors, Institute of Computing Technology, CAS, Sa Wang SKLP, Institute of Computing Technology, Chinese Academy of Sciences; University of Chinese Academy of Sciences, David Boland The University of Sydney, Yungang Bao State Key Lab of Processors, Institute of Computing Technology, CAS; University of Chinese Academy of Sciences, Kan Shi Institute of Computing, Chinese Academy of Sciences

Sat 31 Jan
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Collaroy										Workshops and Tutorials XiangShan																											Workshops and Tutorials XiangShan																																	Workshops and Tutorials HPSmartNet																											Workshops and Tutorials HPSmartNet

Sun 1 Feb
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Collaroy										Workshops and Tutorials MCCSys																											Workshops and Tutorials MCCSys																																	Workshops and Tutorials MCCSys																											Workshops and Tutorials MCCSys

Mon 2 Feb
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Collaroy											Main Conference Cache Coherence and Chiplet Interconnects																				Main Conference DRAM Security and Reliability																																Main Conference Memory System Reliability																				Main Conference Processing-in-Memory Architectures

Tue 3 Feb
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Collaroy											Main Conference CPU Microarchitecture Optimization																				Main Conference Caching and Prefetching																																Main Conference Memory Systems for Scalable Computing																				Main Conference Accelerator Design and Modeling

Wed 4 Feb
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Room	9:00						30						10:00						30						11:00						30						12:00						30
Collaroy											Main Conference Hardware Security and Side-Channel Defenses																				Main Conference FPGA, SmartNIC, and Reconfigurable Computing

Mon 2 Feb
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Room	9:00			15			30			45			10:00			15			30			45			11:00			15			30			45			12:00			15			30			45			13:00			15			30			45			14:00			15			30			45			15:00			15			30			45			16:00			15			30			45			17:00			15			30			45
Collaroy											HPCA Main Conference $C^3$ : CXL Coherence Controllers for Heterogeneous Architectures 09:50 - 10:10				HPCA Main Conference Cohet: A CXL-Driven Coherent Heterogeneous Computing Framework with Har ... 10:10 - 10:30				HPCA Main Conference Supporting High-performance Write-through Cache-Coherence Protocols und ... 10:30 - 10:50				HPCA Main Conference Deadlock-Free Bridge Module for Inter-Chiplet Communication in Open Chi ... 10:50 - 11:10								HPCA Main Conference MIRZA: Efficiently Mitigating Rowhammer with Randomization and ALERT 11:30 - 11:50				HPCA Main Conference SALT: Track-and-Mitigate Subarrays, Not Rows, for Blast-Radius-Free Row ... 11:50 - 12:10				HPCA Main Conference ReScue: Reliable and Secure CXL Memory 12:10 - 12:30				HPCA Main Conference Secret Caching Sauce for High-Performance Secure Memory 12:30 - 12:50																				HPCA Main Conference Predicting DRAM Failures at Scale: A Two-Stage Approach for Heterogeneo ... 14:10 - 14:30				HPCA Main Conference MemSOS: OS-Guided Selective Memory Mirroring 14:30 - 14:50				HPCA Main Conference ASPA: Reassigning DDR5 Parity Bandwidth 14:50 - 15:10				HPCA Main Conference HR-DCIM: \underline{H}igh-\underline{R}eliability Floating-Point \under ... 15:10 - 15:30								HPCA Main Conference The Memory Processing Unit: A Generalized Interface for End-to-End In-M ... 15:50 - 16:10				HPCA Main Conference CoCoTree: A Computation-Capable Architecture for Collective Communicati ... 16:10 - 16:30				HPCA Main Conference PIM-malloc: A Fast and Scalable Dynamic Memory Allocator for Processing ... 16:30 - 16:50				HPCA Main Conference Count2Multiply: Reliable In-Memory High-Radix Counting 16:50 - 17:10

Tue 3 Feb
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Collaroy											HPCA Main Conference The Last-Level Branch Predictor Revisited 09:50 - 10:10				HPCA Main Conference Tempranillo: Non-Speculative Early Register Release 10:10 - 10:30				HPCA Main Conference SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Ef ... 10:30 - 10:50				HPCA Main Conference I-POP: Ignite Positive Prefetchers 10:50 - 11:10								HPCA Main Conference Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online ... 11:30 - 11:50				HPCA Main Conference Streamlined On-Chip Temporal Prefetching 11:50 - 12:10				HPCA Main Conference Intermittence-Aware Cache Compression 12:10 - 12:30				HPCA Main Conference SnakeMan: Applying Relation-centric Notation to Model and Optimize Data ... 12:30 - 12:50																				HPCA Main Conference BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism 14:10 - 14:30				HPCA Main Conference RoMe: Row Granularity Access Memory System for Large Language Models 14:30 - 14:50				HPCA Main Conference HDPAT: Hierarchical Distributed Page Address Translation for Wafer-Scal ... 14:50 - 15:10				HPCA Main Conference Pulse: Fine-Grained Hierarchical Hashing Index for Disaggregated Memory 15:10 - 15:30								HPCA Main Conference NPUWattch: ML-based Power, Area, and Timing Modeling for Neural Acceler ... 15:50 - 16:10				HPCA Main Conference Area Bloating and the Future of Specialization 16:10 - 16:30				HPCA Main Conference Advancing Full-stack Acceleration for Schrödinger-Style Quantum Simulation 16:30 - 16:50				HPCA Main Conference COMET: Communication and Memory Co-Design for Fine-Grained AI Inference ... 16:50 - 17:10

Wed 4 Feb
Displayed time zone: Hobart change


Room	9:00			15			30			45			10:00			15			30			45			11:00			15			30			45			12:00			15			30			45
Collaroy											HPCA Main Conference DSASSASSIN: Cross-VM Side-Channel Attacks by Exploiting Intel Data Stre ... 09:50 - 10:10				HPCA Main Conference SSBleed: Non-speculative Side-channel Attacks via Speculative Store Byp ... 10:10 - 10:30				HPCA Main Conference Protean: A Programmable Spectre Defense 10:30 - 10:50				HPCA Main Conference HERO-Sign: Hierarchical Tuning and Efficient Compiler-Time GPU Optimiza ... 10:50 - 11:10								HPCA Main Conference RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs 11:30 - 11:50				HPCA Main Conference DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Progr ... 11:50 - 12:10				HPCA Main Conference Sassy: SmartNIC-Assisted Notification Delivery for μs-scale RDMA Workloads 12:10 - 12:30				HPCA Main Conference TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verifi ... 12:30 - 12:50

Room information: Collaroy

This program is tentative and subject to change.

Sat 31 Jan
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Sun 1 Feb
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Mon 2 Feb
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Sat 31 Jan
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Workshops and Tutorials

Workshops and Tutorials

Workshops and Tutorials

Workshops and Tutorials

Sun 1 Feb
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Workshops and Tutorials

Workshops and Tutorials

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Mon 2 Feb
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Main Conference

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Tue 3 Feb
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Tracks

HPCA/CGO/PPoPP/CC 2026

Co-hosted Conferences

Room information: Collaroy

This program is tentative and subject to change.

Program Display Configuration

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