Modern HBM-based memory systems have evolved over successive generations while retaining cache line granularity accesses. Preserving this fine granularity has required the introduction of bank groups and pseudo channels, which expand timing parameters and control overhead, thereby increasing the scheduling complexity of the memory controller. Large Language Models (LLMs) now dominate machine learning workloads and stream contiguous data blocks ranging from several kilobytes to several megabytes per operation. In a conventional HBM-based memory system, it must be divided into hundreds of 32B cache line transfers, forcing the MC to employ unnecessarily intricate scheduling and leading to growing inefficiency. To address this problem, we propose RoMe. RoMe accesses DRAM at row granularity and removes columns, bank groups, and pseudo channels from the memory interface. This design reduces the number of bank states and timing parameters and dramatically shrinks the depth of request queue otherwise required for reordering. Despite these simplifications, RoMe maintains the performance of representative LLM workloads, demonstrating that it can streamline an HBM-based memory system without performance loss and offering a practical alternative for future generations.