Multi-GPU systems deliver high memory capacity and computing power but suffer from slow inter-GPU communication. Wafer-scale GPUs provide a promising solution to the scalability challenge by connecting numerous GPUs with a high-bandwidth and low-latency interposer-based network. While prior work has prototyped wafer-scale GPUs to demonstrate technical feasibility, limited research focuses on architectural designs required to harness the power of such massive devices. With the large number of chiplets and the large-scale interconnect, new bottlenecks emerge that differ from those previously identified in traditional multi-GPU systems. Specifically, the virtual-to-physical address translation process has become a critical constraint in wafer-scale GPU systems due to 1) massive concurrent translation requests and 2) long multi-hop latency in the network. To address these issues, we propose HDPAT, a solution to alleviate translation pressure and enable GPU chiplets to locate the required physical addresses efficiently. HDPAT leverages the GMMUs in other chiplets to improve the concurrency of translation. Moreover, as the translation requests are eventually resolved in the center chiplet (CPU), we convert the close-to-center chiplets to double as translation caches to surrounding chiplets. Additionally, to reduce compulsory misses, HDPAT develops page table entry prefetching. Experimental results on 13 representative applications indicate that HDPAT improves overall performance by an average of 57.99% with negligible area overhead 4.22% of GPU L2 Cache for cuckoo filter and 0.26% of GPU L2 Cache for Next-Hop Computation Unit.