Sassy: SmartNIC-Assisted Notification Delivery for μs-scale RDMA Workloads
RDMA is the preferred ultra-low-latency transport in modern datacenters. As services decompose into latency-critical microservices, servers maintain hundreds to thousands of connections across tiers. However, RDMA’s polling-based RPC notification struggles at high core and connection counts, forcing a tradeoff between idle polling, inter-core synchronization costs, and load imbalance—each limiting throughput for \microsecond-scale services. We introduce Sassy, a smartNIC-based notification mechanism that breaks this tradeoff, optimizing the performance and scalability of servicing \microsecond-scale RPCs over high connection counts. Sassy eliminates performance overheads stemming from idle polling and inter-core synchronization, while balancing the load of active RDMA connections across available cores. We implement Sassy on an FPGA-enhanced NIC and evaluate it on a range of traffic patterns, as well as a high-performance key-value store. For deployment scenarios with high connection counts, Sassy improves throughput under SLO by up to 2.3$\times$.
Wed 4 FebDisplayed time zone: Hobart change
11:30 - 12:50 | FPGA, SmartNIC, and Reconfigurable ComputingMain Conference at Collaroy Chair(s): Jinho Lee Seoul National University | ||
11:30 20mTalk | RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs Main Conference Hongshi Tan National University of Singapore, Yao CHEN , Xinyu Chen Hong Kong University of Science and Technology, Qizhen Zhang University of Toronto, Cheng Chen ByteDance, China, Weng-Fai Wong National University of Singapore, Bingsheng He National University of Singapore | ||
11:50 20mTalk | DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics Main Conference Anshu Gupta UC San Diego, Yingqi Cao UC San Diego, Jason Liang UC San Diego, Yatish Turakhia UC San Diego | ||
12:10 20mTalk | Sassy: SmartNIC-Assisted Notification Delivery for μs-scale RDMA Workloads Main Conference | ||
12:30 20mTalk | TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification Main Conference Yang Zhong Institute of Computing, Chinese Academy of Sciences, Haoran Wu University of Cambridge, Xueqi Li State Key Lab of Processors, Institute of Computing Technology, CAS, Sa Wang SKLP, Institute of Computing Technology, Chinese Academy of Sciences; University of Chinese Academy of Sciences, David Boland The University of Sydney, Yungang Bao State Key Lab of Processors, Institute of Computing Technology, CAS; University of Chinese Academy of Sciences, Kan Shi Institute of Computing, Chinese Academy of Sciences | ||