Overlapping high-current operations in 3D NAND flash memory, scaling beyond 300 wordline (WL) layers, frequently exceed Power Management IC (PMIC) limits in high-density NAND systems, including SSDs and UFS, causing voltage droop, sensing errors, data corruption, or device resets. Existing techniques, like controller-enforced throttling or analog slope control, mitigate peaks but incur performance trade-offs under variable and unpredictable current patterns. We propose a distributed, real-time inter-die interconnection network for cooperative peak current management within NAND packages. Each die integrates a lightweight Peak Power Management (PPM) controller, retrieving pre-configured data of local current estimates and communicating over token-ring or mesh topologies to share high-current phase timing and magnitude information. By coordinating token-granted execution during peak-sensitive operations and allowing free progression in low-current phases, our system eliminates peak current overlaps without sacrificing concurrency. Simulation results demonstrate 100% elimination of peak current violations while preserving 97% of ideal throughput, offering a scalable, power-aware design for high-performance computing in next-generation high-density NAND systems like UFS 5.0.