Toward Scalable Gate-Level Parallelism on Trapped-Ion Processors with Racetrack Electrodes
A recent advancement in quantum computation has demonstrated quantum advantage by using randomized circuits on a racetrack-shaped trapped-ion processor. This work investigates the execution efficiency of this architecture for general-purpose quantum programs, which exhibit different computational characteristics compared to the randomized circuits. We first explore the impact of increasing the number of operational zones on runtime efficiency. Counterintuitively, our evaluations using variational program benchmarks reveal that expanding the number of gate operational zones may degrade runtime performance under existing scheduling policies. This degradation could be attributed to the proportional increase in track length, which increases ion circulation overhead, thereby offsetting the benefits of enhanced gate-level parallelism. To mitigate this, we propose three key strategies for scalable parallel execution on racetrack processors: (i) unitary decomposition and translation to maximize zone utilization, (ii) prioritizing the execution of nearby gates over ion movement, and (iii) implementing shortcuts to provide alternative circulation paths. Our evaluations demonstrate that these strategies improve the runtime performance of variational programs by an average of 71% and that of the error correction-applied programs by an average of 32%. Furthermore, these strategies can ensure that the architectural design remains scalable by maintaining runtime performance even as the number of operational zones increases, even in the worst-case scenarios.