Current multiprocessors that support the total store order (TSO) memory consistency model invariably use write-back (WB) cache-coherence protocols. When their hardware needs to issue write-through (WT) stores as in uncached operations, they deliver dismal performance: writes to main memory have to be fully serialized, often forcing the program to observe the full latency of a round-trip to memory.

To solve this problem, this paper presents a novel architecture that supports high-performance cache-coherent WT stores under TSO. The architecture, called PhasedStore, involves extending the store queue of the core and the directory. Individual WT stores in two phases, which allow them to fully overlap with other stores and still satisfy TSO.

PhasedStore is useful in environments that require a WT cache-coherence protocol. This can be the case in resilience-critical platforms where node failures should not cause the loss of shared program state, or platforms with CPUs and accelerators where programs follow a producer-consumer pattern. This paper evaluates PhasedStore in the first environment, namely a CXL-based distributed shared-memory platform where shared data in the program uses a WT protocol to enable recovery. Our evaluation shows that PhasedStore is very effective. Compared to using the conventional approach to implement WT under TSO, PhasedStore reduces the average execution time of a set of parallel applications by 1.88x.