Scaling fault tolerant quantum computers, especially cryogenic systems, to millions of qubits is very challenging due to poorly-scaling data processing and power consumption overheads. One key challenge is the design of decoders for real-time quantum error correction (QEC), which demands high data rates for error processing; this is particularly apparent in systems with cryogenic qubits and room temperature decoders. In response, cryogenic predecoding using lightweight logic has been proposed to handle common, sparse errors within the cryogenic domain. However, prior work only accounts for a subset of the error sources present in real-world quantum systems with limited accuracy, often degrading performance below a useful level in practical scenarios. Furthermore, prior reliance on SFQ logic precludes detailed architecture-technology co-optimization.

To address these shortcomings, this paper introduces Pinball, a comprehensive design in cryogenic CMOS of a QEC predecoder tailored to realistic, circuit-level noise. By accounting for error generation and propagation through QEC circuits, our design achieves higher predecoding accuracy, outperforming the logical error rate of both the state-of-the-art cryogenic and room-temperature predecoders by more than six orders of magnitude and 38.88$\times$, respectively. By increasing cryogenic coverage, we also reduce syndrome bandwidth up to 5892.75$\times$. Through co-design with 4,K-characterized 22,nm FDSOI technology, we achieve a peak power consumption under 0.54,mW. Voltage/frequency scaling and body biasing enable 22.2$\times$ lower typical power consumption, yielding up to 72.1$\times$ total energy savings. Given a conservative 4,K power budget of 1.5,W, our predecoder can support up to 2,777 logical qubits at $d=21$.